This specification relates to processor architectures.
Some processor architectures can execute multiple independent threads, e.g., multithreading. In some cases, it is desirable for a thread to wait on an input/output (IO) or synchronization operation rather than yielding the thread to a processing core by context switching another thread on the processor core. To accomplish this, software can implement busy polling or spin polling on one or more memory addresses, e.g., spinlock-based synchronization. While busy polling on memory addresses could result in advantageous latency by avoiding context switching overheads, it inevitably results in wasted execution resources. For example, with single-threaded processing cores or hyperthreaded processing cores that lack any hardware thread switching capability, the processing cores could go unused for real work during busy polling, which may waste resources of other hyperthreads on the processing cores. Moreover, if a number of memory addresses being polled is numerous, it may cause additional latency.